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PCIe Lanes & Slots
x16/x8/x4 layouts, bifurcation, risers, and bandwidth planning for builds.
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Low-Cost PCB Enables Automated Device Testing
15+ hour, 37+ min ago (17+ words) An open-hardware test platform combines measurement, switching, and device-testing functions on a modular PCB costing about $790....
Cadence's PCIe 6.0 subsystem clears official compliance testing
1+ day, 14+ hour ago (221+ words) Cadence’s PCIe 6.0 subsystem clears official compliance testing Nasi Lemak Tech Cadence’s latest news comes in the form of its PHY and controller IP for PCIe 6.0 passing official PCI-SIG compliance testing on the very first attempt. PCIe is the backbone connecting…...
Cadence PCIe 6.0 subsystem passes first official compliance testing
1+ day, 19+ hour ago (202+ words) Cadence has announced that its complete PCIe 6.0 subsystem, combining PHY and controller IP, has achieved first-pass compliance with the PCI Express 6.0 specification. The x8 subsystem was tested at the standard’s full 64 GT/s data rate during PCI-SIG’s first official PCIe 6.0 compliance…...
Cadence PCIe 6.0 Clears First-Pass Compliance Testing
1+ day, 20+ hour ago (234+ words) Cadence Design Systems announced that its PHY and controller IP for the PCIe 6.0 specification, implemented on TSMC’s N3 process, achieved first-pass compliance at PCI-SIG’s compliance workshop in late July. The event was the industry’s first official compliance testing round for the…...
Synopsys TestMAX Unified Compression and Streaming Fabric for AI Chip Testing - News and Statistics
1+ day, 11+ hour ago (448+ words) Modern AI and high-performance computing devices are straining conventional test architectures, according to Synopsys. As scan data volume, core counts, chiplet integration and test coverage requirements keep rising, traditional design-for-test methodologies are becoming harder to scale. Synopsys describes its TestMAX…...
Cadence PCIe 6.0 subsystem achieves first-pass compliance certification
1+ day, 14+ hour ago (195+ words) Digital lifestyle, smart devices and gadgets Cadence has announced that its PHY and controller IP for the PCIe 6.0 specification, built on TSMC’s N3 process, achieved first-pass success at the recent PCI-SIG compliance workshop held in late July, the industry’s first official…...
Credo Technology achieves PCI-SIG 6.x compliance for Toucan retimer, eyeing AI infrastructure boom
1+ day, 15+ hour ago (391+ words) The semiconductor firm's latest PCIe retimer hit 64.0 GT/s compliance, a key milestone for next-generation AI accelerator platforms and high-performance computing. Credo Technology Group (NASDAQ: CRDO) announced that its Toucan Gen6x16 PCIe retimer has passed PCI-SIG 6.x compliance testing at 64.0 GT…...
Teradyne Introduces Iris 100: Production-Proven Test System for MicroLED Devices
2+ day, 21+ hour ago (323+ words) Yahoo Finance Oops, something went wrong Teradyne Introduces Iris 100: Production-Proven Test System for MicroLED Devices Delivers semiconductor-grade test for next-generation optical interconnects powering scale-up in AI data centers. NORTH READING, Mass., September 21, 2026--(BUSINESS WIRE)--Teradyne, Inc. (NASDAQ: TER), a leading…...
SignatureIP Unveils MesoLink, a Mesochronous Bridge for PCIe/CXL Validation
1+ week, 5+ hour ago (230+ words) A PCIe/CXL device under test keeps its native generation, lane width and timing; the FPGA side runs full-rate SerDes. Plug-and-play prototyping and emulation. The IP is built around three interfaces: MesoLink is offered as Soft IP, delivered as synthesizable…...
32-channel logic analyzer supports 1.4GS/s sampling and USB 3.2 Gen2 streaming
1+ week, 1+ day ago (484+ words) Sipeed is preparing the SLogic32U3, a compact 32-channel logic analyzer designed for high-speed digital capture over USB 3.2 Gen2. The device supports configurable sample rates based on the number of active channels, direct streaming to a host system, optional analog acquisition modules, and…...